Auteurs: Hichem. Mayache1 3, Salah Toumi1, El Bey Bourennane & Atef. Benhaoues 1
1 LERICA Laboratory, University of Badji-Mokhtar, Po Box 12, Annaba, 23000, Algeria.
2 LE2I Laboratory, University of Bourgogne, Dijon – France.
3 LABGET Laboratory, University of Larbi Tebessi, Tebessa, 12000, Algeria.
Soumis le : 14/12/2017 Révisé le : 09 /06/2018 Accepté le : 11/06/2018
Networks on chip have emerged as new scalable, flexible and reusable On-Chip Interconnect solution for System-on-Chip applications. Inspired from computer networks, they offer a good compromise between cost and performance. In this work, we present a Buffer-less Network-on-Chip for video encoding applications. The main idea is to use a buffer-less NoC to interconnect the IPs composing the H.264/AVC video encoder. The proposed architecture is described using Hardware Description Language onto Virtex-7 XC7V2000T FPGA platform. Thereafter, results are compared to similar works using other interconnect solutions and the implementation shows that the proposed architecture offers a higher maximum frequency operating with a lower logic cost.
Keywords: NoC, SoC, Video Encoder Application, H.264/AVC encoder.