A new technique for accelerating routing information process in communication networks

Numéro de la revue: 32
Auteurs: Ramzi Benaicha & Mahmoud Taibi2

1 L.E.R.I.C.A Laboratory, Badji Mokhtar Annaba University, Po Box 12, 23000, Annaba, Algeria.
2 Automatic and  Signals Laboratory (LASA), Badji Mokhtar Annaba University, Po Box 12,  23000, Annaba, Algeria.

 

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Abstract

The calculation of the shortest path between a pair of routers is an important problem in telecommunication and computer networks. The calculation of the path in real time is useful in a number of situations. These include a routing process that attempts to reach its destination and minimizing the effects of collision with obstacles. Previous works on the shortest path are limited to sequential and parallel algorithms on general-purpose architectures. Researchers are increasingly interested in hardware’s solutions. In this work , we propose an approach for implementing a routing algorithm which is effective than Dijkstra using a FPGA development board Xilinx Virtex-type order accelerate the process of routing based on the speed of hardware (FPGA). The results of the implementation in an FPGA card Virtex7 are promising.

Key words: WLAN, OSPF, Dijkstra algorithm, Language VHDL, FPGA.